The invention relates to the regulation of a clock duty cycle for use in conjunction with Very Large Scale Integration (VLSI) microelectronic circuits.
In the field of VLSI microelectronic circuits, many digital systems require a certain clock duty cycle (i.e. 50/50%, 40/60%) for proper operation. However, such clock duty cycles are not always readily available. A clock with an inappropriate duty cycle may cause the digital system to fail or force the system to run at a lower clock speed. Although many digital systems desire a 50/50% duty cycle, not all digital systems necessarily desire the same clock duty cycle. Depending on the source of the clock, the duty cycle may not always be known or predictable. Hence, duty cycle correction is needed.
One such approach to duty cycle correction is to use a phase-locked loop to synthesize a clock at double the input frequency, and then to divide down by two to obtain a 50/50% duty cycle. This approach requires the building of a phase-locked loop, which is complex in design, large in area, and high in power. This approach also only limits the output duty cycle to 50/50%.
In U.S. Pat. No. 5,317,202, Waizman discloses a 50% duty-cycle clock generator, which is limited to generating only a 50% duty cycle and its implementation complicated. In U.S. Pat. No. 5,572,158, Lee et al describe an amplifier circuit with active duty cycle correction to produce a pre-determined duty cycle. However, such a circuit uses three operational amplifiers, thus being relatively high in power consumption and large in area. In U.S. Pat. No. 5,757,218, Blum describes a circuit and a method for signal duty cycle correction, which involves the use of a ring oscillator counter to produce adjustable delays. In order for this approach to have sufficient duty cycle resolution, the ring oscillator must operate at a frequency much higher than the input clock, meaning a large use of power. Lower operating speeds would mean degradation in the duty cycle resolution.
In U.S. Pat. No. 5,550,499, Eitrheim describes an adjustable duty cycle clock generator using multiplexers to adjust the delay in a delay line. The problem with this approach is that the amount of delay needed is not known by the circuit and must be determined elsewhere either through measurement or other dynamic means. This circuit cannot self-correct for the appropriate duty cycle. In U.S. Pat. No. 5,617,563, Banerjee et al describe a duty-cycle independent tunable clock that uses an adjustable delay line in conjunction with a flip-flop. However, the described circuit is limited by using a fixed delay, once adjusted (by blowing out fuses through a laser), thereby providing a duty cycle for a given adjustment which directly depends on the clock input. Furthermore, the use of blowing out fuses for changing the duty cycle is relatively expensive and demands a larger overall circuit. Once the fuses are set to provide a desired duty cycle for a particular clock frequency, they cannot be changed again to operate with a different frequency or to obtain a different duty cycle.
In U.S. Pat. No. 5,477,180, Chen describes a circuit and a method for generating a clock signal wherein the duty cycle is adjusted independent of the input clock frequency by adjusting a bias voltage at the driver circuit of the output clock, which is driven by the input clock. This bias voltage is generated by a differential amplifier driven by two voltage-adjusted inputs using two adjustable tapped resistors. In Chen""s approach, however, at least one operational amplifier and four resistors are required resulting in a relatively large circuit area and high power. Furthermore, the resulting output clock signal is shaped by an RC time constant giving relatively long rise/fall times, especially when duty cycles far beyond 50/50% are desired. Chen teaches that for duty cycles far beyond 50/50%, a few of the described circuits can be cascaded for better rise/fall times. This would require more operational amplifiers and more resistors, hence larger circuit size and greater power consumption. Moreover, there is no provision in Chen""s approach for adjusting the duty cycles xe2x80x98on the flyxe2x80x99, i.e. whenever desired by the user.
In view of the limitations of the prior art reviewed above, it would be desirable to provide an economical circuit and method for regulating a steady state clock duty cycle over a relatively wide range of selectable duty cycles, without being dependent on an actual input clock frequency value.
An object of this invention is to provide a duty cycle regulator for providing an output clock signal having a preselected duty cycle.
In accordance with an aspect of the present invention, there is provided a duty cycle regulator for providing an output clock signal having a pre-selected duty cycle. The duty cycle regulator includes a clock pulse generator, a flip-flop circuit and a delay circuit. The clock pulse generator has a clock edge detector for generating a clock pulse signal in response to a leading edge of an input clock signal. The flip-flop circuit has a set input coupled to the clock pulse signal, a reset input coupled to a reset signal, and an output port for providing the output clock signal. The delay circuit receives the input clock signal and the output clock signal for generating the reset signal after the flip-flop-circuit is set to a first state, and the reset signal has an adjustable duration which is a fraction of the period of the input clock signal.
In accordance with another aspect of the present invention, there is provided a duty cycle regulator for providing an output clock signal having a predetermined duty cycle. The duty cycle regulator includes a clock pulse generator, a flip-flop circuit, and a delay circuit. The clock pulse generator has a clock edge detector responsive to a leading edge of an input clock signal, where the clock pulse generator provides a pulse signal when the leading edge is detected. The flip-flop circuit has a set input port for receiving the pulse signal, a reset input coupled to a reset signal, and an output port for generating the output clock signal. The delay circuit receives the output clock signal and generates the reset signal after an adjustable time delay determined by the duty cycle of the output signal and control current, such that the delay circuit generates the reset signal after the flip-flop-circuit is set to a first state.
In accordance with yet another aspect of the present invention, there is provided a pulse generator circuit for generating an adjustable duration pulse. The pulse generator includes a first transistor, a second transistor, an amplifier, and a third transistor. The first transistor has its source coupled to a voltage supply, its drain coupled to a first node, and its gate coupled to a clock signal. The second transistor has its source coupled to the first node, its drain coupled to a third transistor, and its gate coupled to the clock signal. The amplifier is coupled to the first node for providing the adjustable duration pulse, and the amplifier has a predetermined threshold voltage. The third transistor has its source coupled to a ground potential, and its gate coupled to a voltage control signal, such that the voltage control signal is responsible for lowering a voltage potential on the first node to a voltage lower than the predetermined threshold voltage.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.